Verilog by Example: A Concise Introduction for FPGA Design - Blaine Readler - Kirjat - Full ARC Press - 9780983497301 - tiistai 19. huhtikuuta 2011
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Verilog by Example: A Concise Introduction for FPGA Design

Blaine Readler

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Verilog by Example: A Concise Introduction for FPGA Design

A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with "The Elements of Style," VERILOG BY EXAMPLE does for FPGA design.


black & white illustrations

Media Kirjat     Paperback Book   (Kirja pehmeillä kansilla ja liimatulla selällä)
Julkaisupäivämäärä tiistai 19. huhtikuuta 2011
ISBN13 9780983497301
Tuottaja Full ARC Press
Sivujen määrä 124
Mitta 229 × 151 × 11 mm   ·   200 g
Kieli English  

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