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SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications Ashok B. Mehta 2014 edition
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SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications
Ashok B. Mehta
Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'.
234 pages, 260 black & white illustrations, 5 black & white tables, biography
| Media | Kirjat Hardcover Book (Sidottu kirja kovilla kansilla sekä suojakannella) |
| Julkaisupäivämäärä | tiistai 6. elokuuta 2013 |
| ISBN13 | 9781461473237 |
| Tuottaja | Springer-Verlag New York Inc. |
| Sivujen määrä | 356 |
| Mitta | 155 × 235 × 22 mm · 721 g |
| Kieli | Englanti |
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