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Logic Synthesis and SOC Prototyping: RTL Design using VHDL Vaibbhav Taraate 2020 edition
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Logic Synthesis and SOC Prototyping: RTL Design using VHDL
Vaibbhav Taraate
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.
251 pages, XIX, 251 p.
| Media | Kirjat Paperback Book (Kirja pehmeillä kansilla ja liimatulla selällä) |
| Julkaisupäivämäärä | lauantai 30. tammikuuta 2021 |
| ISBN13 | 9789811513169 |
| Tuottaja | Springer Verlag, Singapore |
| Sivujen määrä | 251 |
| Mitta | 150 × 220 × 10 mm · 500 g |
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