Modeling Multi-processor Systems at Transaction-level: a Versatile Approach to Hardware Architectures Design and Testing

In recent years embedded systems have gained a widespread diffusion both in every market; anyone of us get in touch with them several times a day. Often even without noticing them. Power dissipation, difficulties in increasing the clock frequency, and the need for technology reuse to reduce time-to-market push towards new solutions, such as exploiting inherent application parallelism, running them on multiple standard processor cores. This brought to the definition of Multi-Processor System-on-Chip (MPSoC). Their design raises new challenges due to the large design space and tight design and time-to-market constraints. MPSoC are complex devices and therefore require some particular modeling techniques in order to hide their inherent complexity, without loosing in model accuracy and flexibility. This work approaches two different aspects of MPSoCs design. This is intended to provide an overview of concerns and a comparison with the specific literature of the different fields involved and, at the same time, simplifying the overall MPSoC design problem considering it separately.