Transient Faults in Quasi Delay-insensitive Logic: Effects and Mitigation

Asynchronous Quasi Delay-Insensitive (QDI) logic offers an improved fault tolerance compared to synchronous logic. Its delay-insensitive encoding makes it not only robust to varying delays but also highly insensitive to transient faults. This work introduces a new trace based transient fault model that covers both unprotected as well as hardened QDI circuits in the necessary level of detail with moderate computational efforts. Using that model, new hardening methods for QDI circuits based on the principle of "duplication and rail cross-coupling" are derived. The proposed hardening methods are assessed by means of simulation and hardware based fault injection. Two customized fault injection tools are developed that overcome the limitations of existing tools in such fields. Several basic test circuits as well as one moderately complex signal processing application are selected to verify the predicted fault tolerance of the different hardening strategies. It is shown that a clever re-arrangement of a duplicated QDI circuit helps to improve the tolerance against transient faults significantly, while keeping the hardware overhead low.