Umesh T. H.

Rsa Cryptosystem: Asic Implementation Using Cadence Umesh T. H.

This work provides an insight on the implementation of RSA cryptosystem using Verilog finally resulting in an IC. The complete implementation includes three phases: key generation, encryption process and decryption process. To generate the key, we use Random Number Generator and GCD blocks. Whereas for Encryption and Decryption processes Modular Multiplication, Modular Exponentiation blocks were implemented. Finally to bring out an IC, SoC Encounter in Cadence is used. The work also emphasizes on an introduction to Cadence and Verilog. Implementation details of some basic systems in Cadence using Verilog are also highlighted.